Parallel systems such as artificial neural networks or pixel arrays often rely on localized mathematical operations performed in distributed unit cells in one, two, or three-dimensional arrays. One fundamental mathematical element necessary to many mathematical operations is the counter element. Counters are used to accumulate input signals, apply multiplication factors, integrate over time and generally assist in many types of temporal operations. It is advantageous for these computations and the subsequent results to be self-contained in the unit cell to reduce information transfer, thereby increasing the speed and reducing the power necessary to complete each operation. One example of an image sensing application making use of small area counters is arrayed digital pixel sensors. These sensors often rely on very small signal accumulators made out of count elements to store the integrated signal captured within a scene. In digital pixel sensors, an analog input to the unit cell is converted to a digital word that can be manipulated and stored via digital gates and flip-flops. See, e.g., B. Fowler, et al., “A CMOS Area Image Sensor With Pixel Level A/D Conversion,” IEEE Int'l Solid-State Circuits Conference, pp. 226-227 (1994).
There are multiple ways to make an analog counter. The most straight forward way is to pulse a current source for a set amount of time so as to deposit charge on a capacitor for each pulse. See, e.g., K. Madani, et al., “Two analog counters for neural network implementation,” IEEE J. Solid-State Cir., vol. 26, no. 7, pp. 966-974 (July 1991). The final voltage left on the capacitor will be linearly proportional to the number of pulses or counts. The problem with this scheme is that the charge packet deposited on the capacitor each time is a function of both the current magnitude as well as the pulse width. This reduces the maximum resolution of an analog counter by increasing the noise floor and generally makes this architecture less robust. This method is also prone to signal-dependent resistive drop cross-talk across large arrays of elements, thereby further degrading the achievable count.
Other methods rely on precision charge transfer mechanisms. This typically requires a precision voltage supply to set a voltage across a charge transfer capacitor, which has some of the same speed and supply management issues for large arrays as in conventional digital pixel architectures.
Prior work has shown that capacitors can serve as analog storage devices with reduced power and area compared to their digital counterparts. See, e.g., D. Stoppa, et al., “A 32×32-Pixel Array with In-Pixel Photon Counting and Arrival Time Measurement in the Analog Domain,” IEEE European Solid-State Device Conference, pp. 204-207 (2009). Unfortunately, logarithmic behavior and non-binary weighting inherently reduce the noise margin for interpreting the stored values. Further, chip-wide mismatch and charge transfer nonlinearity amplify the complexity while reading out an array of analog stored values. Cascaded analog counters have been shown to alleviate the noise margin constraint by storing the data on several rank-weighted capacitors. See, e.g., A. Peizerat, et al., “An analog counter architecture for pixel-level ADC,” Proc. of 2009 Int'l Image Sensor Workshop, Bergen, NORWAY (Jun. 22-28, 2009). While previous efforts have presented charge-packet transfer techniques for fixed analog step sizes, there is a need to develop a novel architecture that exhibits improved step size linearity and uniformity across the array as well as improved bias management for large arrays.